Profile
Passionate about designing efficient, fault-tolerant ML hardware systems and neuromorphic computing architectures. Expertise in radiation-hardened ASICs, high-level synthesis, and training-aware hardware accelerators. Enthusiastic about bridging the gap between machine learning and physical implementation challenges.
ASIC VLSI RAS FPGA ML accelerators HLS Digital Design Verification PyTorch SystemVerilog Cadence EDA
Education
Northwestern University
Computer Engineering
Ph.D. in Computer Engineering
GPA 3.9/4.0
Hardware-software co-designed ML systems, neuromorphic learning, and radiation-hardened ASICs.
Thesis: In progress.
Northwestern University
Computer Engineering
M.S. in Computer Engineering
GPA 3.9/4.0
Completed graduate coursework in ASIC design, ML accelerators, and digital systems.
CBPF
Brazilian Center for Physics Research
M.S. in Physics & Scientific Instrumentation
GPA 3.8/4.0
UPC BarcelonaTech
Polytechnical University of Barcelona
B.S. in Robotics & Electronics Engineering
GPA 3.3/4.0
Work experience
AMD
Reliability, Availability, and Serviceability
Systems Engineer Junior - RAS
- Developing techniques to evaluate resilience of high-performance processors under delay/fault scenarios.
- Building ML/data-analysis pipelines to extract trends from reliability datasets.
- Collaborating with system and hardware architects on mitigation strategies.
Northwestern University / Fermilab / CERN
ASIC + ML Accelerator Research
ASIC + ML Accelerator Researcher
- Developing NRCST K: a neuromorphic learning system with local learning rules and metabolic optimization.
- Led multiple ASIC efforts across GF 22nm FD-SOI, TSMC 28nm, and TSMC 65nm processes (RTL/HLS to P&R to signoff).
- Built reusable automation for synthesis, P&R, extraction, and signoff (Cadence Virtuoso/Innovus/Genus/Tempus/Voltus).
- Implemented radiation-hardened logic with TMR; developed RTL tools for redundancy injection.
- Extended ENABOL: training-aware HLS templates and backward-pass wrappers for training-capable hardware.
Cadence Design Systems
Timing / EDA
Tempus SSV Graduate Intern
- Researched silicon aging/drift impacts in 5nm CMOS and their effects on timing closure.
- Developed and integrated drift estimation modules into Tempus SSV.
- Created tooling for drift-aware library characterization and algorithm improvements.
- Explored ML-assisted prediction techniques for drift-aware analysis.
Petrobras
Deep Learning and Reservoir Characterization
Deep Learning Specialist
- Built and deployed CNN/autoencoder/Bayesian deep learning models for industrial imaging and reservoir characterization.
- Delivered end-to-end pipelines: data ingestion, training/evaluation, uncertainty quantification, production reporting.
- Developed AI systems for oil & gas reservoir characterization using seismic and borehole image data.
- Applied Bayesian deep learning for uncertainty quantification and model robustness.
CERN INFIERI School
Universidad Autonoma de Madrid
ASIC Design & Verification Lecturer (Invited Instructor)
- Delivered 5-day lecture/lab series on ASIC design & verification (synthesis, P&R, DRC/LVS, signoff) to international cohort of ~20+ students.
- Developed academic labs and automated flows covering full design methodology.
Skills
Programming
ML & AI
ASIC / EDA
HLS / FPGA
Operating Systems
Languages
Spanish native Catalan native Portuguese native-like English fluent French basic
Publications
ML Accelerators
8- Toward Reconfigurable In-Pixel Computing: A Fault-Tolerant Design Flow for Machine Learning Accelerators
- hls4ml: A flexible, open-source platform for deep learning acceleration on reconfigurable hardware
- hls4ml: An open-source codesign workflow to empower scientific low-power machine learning devices
- ECONAI-CMS v1
- CryoAI v1
- CryoAI v2 - Quantum Control ML Accelerator
- 🤖 ENABOL: Enabling Neural Backpropagation On-chip Learning for Edge AI Systems
- 🤖 CryoAI – Prototyping cryogenic chips for machine learning at 22nm
HEP Detectors
9- Smart Pixels: In-pixel AI for on-sensor data filtering
- Radiation-Hard Smart-Pixel Detector ASIC ReadOut with Digital AI in 28nm
- Smart Pixels: Algorithm design and hardware testing for a 28m ROIC for future pixel trackers
- In-pixel AI for lossy data compression at source for X-ray detectors
- Smartpixels: Towards on-sensor inference of charged particle track parameters and uncertainties
- A reconfigurable neural network ASIC for detector front-end data compression at the HL-LHC
- Sprocket v1 - xray imaging
- In-Pixel AI v1 - Photon Science Detector
- CMS28v2 – AI In-Pixel Readout Chip for HL-LHC
Quantum & Cryogenic Systems
6- An Ultra-Low-Voltage, 16-Channel Current DAC ASIC in 22nm FDSOI for cryogenic SQUID Biasing
- A cryogenic readout ic with 100 ksps in-pixel adc for skipper ccd-in-cmos sensors
- Neural network accelerator for universal quantum control
- A Cryogenic Readout IC with 100 KSPS in-Pixel ADC for Skipper CCD-in-CMOS Sensors [Poster]
- CITC2 - Cryogenic Mixed-Signal Readout ASIC
- 📟 A Cryogenic Readout IC with 100 KSPS in-Pixel ADC for Skipper CCD-in-CMOS Sensors - Fermilab 2021
Neuromorphic Systems
1Petrophysics & Imaging
7- Bayesian deep networks for absolute permeability and porosity uncertainty prediction from image borehole logs from Brazilian carbonate reservoirs
- Automatic detection of fractures and breakouts patterns in acoustic borehole image logs using fast-region convolutional neural networks
- A deep residual convolutional neural network for automatic lithological facies identification in Brazilian pre-salt oilfield wellbore image logs
- Estimation of permeability and effective porosity logs using deep autoencoders in borehole image logs from the Brazilian pre-salt carbonate
- Porous medium permeability estimation for well imagery and characterization using complex resistivity spectra
- On a method for Rock Classification using Textural Features and Genetic Optimization
- Rock Texture Classification Using Spectral Analysis And Genetically Optimized Texture Features
Astrophysics
3Theses & Technical Notes
4Peer review
Verified peer reviews
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
3 reviews
Patents
Patent
Method of automatic characterization and removal of pad artifacts in ultrasonic images of wells
Patent application for automatic characterization and removal of pad artifacts in ultrasonic images of reservoir wells.
Patent on analysis methods using sensitivity characteristic data and hardware measurement data
BR102018009637A2
Brazilian patent application for automatic detection and characterization of breakouts in reservoir well images.
Talks
Poster on neuromorphic learning systems and ASIC design for neuroscience applications.
Talk on ENABOL for on-chip learning in edge AI systems.
Radiation-Hard Smart-Pixel Detector ASIC ReadOut with Digital AI in 28nm.
Smart pixel sensors: towards on-sensor filtering of pixel clusters with deep learning.
Talk on CryoAI, a 22nm cryogenic chip prototype for machine-learning workloads.
Talk
📟 A Cryogenic Readout IC with 100 KSPS in-Pixel ADC for Skipper CCD-in-CMOS Sensors - Fermilab 2021
Technical presentation on a cryogenic readout IC with in-pixel ADC for Skipper CCD-in-CMOS sensors.
Teaching
Short course / Workshop
ASIC Design & Verification Lecturer (Invited Instructor)
Invited instructor for a 5-day lecture/lab series covering ASIC design, verification, P&R, DRC/LVS, and signoff.