CITC2 - Cryogenic Mixed-Signal Readout ASIC
Published:
CITC2 - Cryogenic Mixed-Signal Readout ASIC
| Field | Value |
|---|---|
| Project | CITC2 - Cryogenic Mixed-Signal Readout ASIC |
| Year | 2023 |
| Technology | 22nm FD-SOI |
| Type | ASIC |
| Status | Taped Out |
| Funding | Northwestern University, Fermilab |
Project Overview
Developed digital controller, configuration interface, and SPI readout for mixed-signal cryogenic ASIC in 22nm FD-SOI. Led RTL-to-GDSII backend flow achieving 200MHz timing closure under cryogenic (4K) constraints.
Design Flow
- RTL Design: Verilog HDL implementation and verification
- Synthesis: Cadence Genus with technology-specific optimization
- Place & Route: Cadence Innovus with timing and power closure
- Physical Verification: DRC/LVS with Calibre and extraction
- Verification: Post-layout simulation and formal verification
GitHub repository: [Add link when available]
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