Manu Blanco Valentin

Manu Blanco Valentin

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Hardware

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... ASIC CMS28v2 – AI In-Pixel Readout Chip for HL-LHC Radiation-hard in-pixel AI filtering for the HL-LHC upgrade 2023 Full digital logic and layout of a radiation-hard pixel ASIC in 28nm CMOS with integrated neural network classifiers HEP ASIC In-Pixel AI AI Accel. Compression RadHard TMR TSMC 28nm hls4ml Arch. RTL ASIC Design Verification Tapeout Project details CERN Fermilab Northwestern University Columbia University
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Description

Designed and implemented the full digital logic and layout for a radiation-hardened pixel ASIC in 28nm CMOS. Integrated neural network classifiers using hls4ml and Catapult HLS to achieve sub-10ns latency with minimal area footprint. This chip is designed for the HL-LHC detector upgrade at CERN to perform on-sensor AI-based filtering of pixel cluster data in real-time.

Key accomplishments:

  • Full RTL-to-GDS II backend flow with timing closure at target clock frequencies
  • Sub-10ns neural network inference latency
  • Radiation-hardened design patterns for HL-LHC environment
  • Integration with detector front-end electronics
  • Production-ready design for fabrication
CITC2 - Cryogenic Mixed-Signal Readout ASIC ASIC CITC2 - Cryogenic Mixed-Signal Readout ASIC Cryogenic mixed-signal controller and SPI readout ASIC 2023 Digital controller and readout for mixed-signal cryogenic ASIC with 200MHz timing Quantum Cryo Control ASIC Readout Mixed Signal GF 22nm RTL ASIC Design Verification Tapeout Project details Fermilab Northwestern University
CITC2 - Cryogenic Mixed-Signal Readout ASIC
Description

Digital controller and readout for mixed-signal cryogenic ASIC with 200MHz timing

CryoAI v2 - Quantum Control ML Accelerator ASIC CryoAI v2 - Quantum Control ML Accelerator Low-power cryogenic accelerator for quantum readout and control 2022 Low-power ML accelerator for quantum readout and control in cryogenic environment Quantum Cryo Control ASIC AI Accel. Readout GF 22nm Arch. RTL ASIC Design Verification Tapeout Project details Fermilab Northwestern University Columbia University
CryoAI v2 - Quantum Control ML Accelerator
Description

Low-power ML accelerator for quantum readout and control in cryogenic environment

... ASIC In-Pixel AI v1 - Photon Science Detector In-pixel neural-network compression for scientific detectors 2022 ML-based compression accelerator for photon science and particle detection Photon Imaging ASIC In-Pixel AI AI Accel. Compression TSMC 65nm Arch. RTL ASIC Design Verification Tapeout Project details Fermilab Northwestern University
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Description

ML-based compression accelerator for photon science and particle detection

... ASIC Sprocket v1 - xray imaging Radiation-hard anomaly-detection accelerator for particle physics 2022 Radiation-tolerant ML accelerator for on-edge anomaly detection in particle physics HEP Imaging ASIC AI Accel. Anomaly TSMC 65nm Arch. RTL ASIC Design Verification Tapeout Project details Fermilab Northwestern University
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Description

Radiation-tolerant ML accelerator for on-edge anomaly detection in particle physics

ECON-I 2021 V1 chip mounted on a printed circuit board ASIC CryoAI v1 Cryogenic ML Accelerator 2021 Ultra-low-power ML accelerator with custom cryogenic memories and RISC-V Quantum Cryo ASIC AI Accel. GF 22nm Arch. RTL ASIC Design Verification Tapeout Project details Fermilab Northwestern University Columbia University
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Description

Ultra-low-power ML accelerator with custom cryogenic memories and RISC-V

ECON-I 2021 V1 chip mounted on a printed circuit board ASIC ECONAI-CMS v1 CMS Calorimeter AI Accelerator 2021 Reprogrammable AI accelerator for CMS calorimeter with radiation hardening HEP ASIC AI Accel. Compression RadHard TMR TSMC 65nm Arch. RTL ASIC Design Verification Tapeout Project details CERN Fermilab Northwestern University Columbia University
Project images
ECON-I 2021 V1 chip mounted on a printed circuit board
ECON-I 2021 V1 chip mounted on a printed circuit board.
Block diagram of the ECONAI-CMS converter, I2C configuration block, and encoder neural network
Architecture overview: converter, distributed I2C configuration block, and encoder neural network.
Annotated physical layout of the ECONAI-CMS chip
Annotated physical layout showing the converter, encoder neural network, and distributed I2C weights.
Register-level triple modular redundancy diagram
Register-level triple modular redundancy with a majority voter.
Full triple modular redundancy diagram
Full triple modular redundancy with replicated combinational logic and majority voters.
Description

On-chip reprogrammable AI accelerator for the CERN CMS calorimeter, implemented in TSMC 65nm. The design handles extreme detector data rates and includes automatic triple modular redundancy injection for radiation hardening.