Computer engineer working at the intersection of artificial intelligence, and hardware mixed-signal design, for the next-generation adaptive on-chip learning ASIC/FPGA.

Electronics, automation, and physical systems

My path started in Barcelona, where I obtained my degree in Electronic and Automation Engineering. That training gave me my first engineering foundation across circuits, control, physical systems, instrumentation, and software.

Applied AI and scientific instrumentation

In 2014, I moved to Rio de Janeiro, Brazil and started working at Petrobras, where I applied deep learning to petrophysics and geoscience problems. I developed methods for borehole image analysis, reservoir characterization, fracture and breakout detection, and uncertainty estimation. This was my first exposure to AI as an engineering tool for scientific and industrial environments.

From AI models to silicon

In 2020, I moved to Chicago, Illinois to begin my Ph.D. in Computer Engineering at Northwestern University, through hardware design work connected to Fermilab and high-energy physics instrumentation. That period shifted my work from using AI models to understanding how they become real hardware: ASIC design, FPGA development, digital implementation, mixed-signal constraints, verification, and low-latency inference for detector systems.

Reliability under extreme constraints

Through collaborative projects with Fermilab and CERN, I worked on hardware intended for environments where reliability is not optional. High-energy physics systems must tolerate radiation, tight latency budgets, and strict implementation constraints, which pushed me toward radiation-aware design, redundancy, fault tolerance, and reliability-aware architecture.

Silicon aging, cryogenics, and signoff reality

As my Ph.D. progressed, I became increasingly interested in how physical operating conditions shape hardware design. The cryoAI chip explored machine-learning hardware for cryogenic quantum-control environments, where computation must operate close to the devices being controlled. In 2023, I also interned at Cadence, working on silicon aging and reliability characterization, which strengthened my understanding of timing, signoff, PVT variation, and device degradation.

On-device reprogrammability and trainability

Many of the neural-network accelerators I worked with were inference-only, or supported only limited weight reprogrammability. That limitation became the motivation for my work on on-device training and adaptation. Projects such as hls4ml-trainable and ENABOL grew from that question: how can we make neural-network accelerators not only fast and efficient, but also trainable, stable, and reliable on constrained hardware?

\(\mathcal{NRCSTK}\): toward autonomous on-device learning

My most recent work pushes that progression further, from conventional trainability toward local, unsupervised, and bio-inspired learning for silicon systems. \(\mathcal{NRCSTK}\), the core direction of my thesis, explores whether local rules tied to physical and thermodynamic properties of the substrate can support autonomous adaptation on device, without relying on centralized backpropagation or offline retraining.

Reliability at CPU scale

In parallel with my Ph.D. research, I am currently interning at AMD, working on reliability, availability, and serviceability architecture for consumer CPUs. This connects naturally with the broader theme of my work: building computing systems that remain useful when algorithms meet real hardware constraints.