ASIC Design & Verification Lecturer (Invited Instructor)

Delivered a 5-day lecture + hands-on lab series on end-to-end ASIC design and verification to an international cohort (~20+ students).

Topics covered

• RTL design methodology (Verilog)
• Testbenching & verification strategy
• Synthesis and timing closure
• Place & Route (P&R)
• Physical verification: DRC/LVS, extraction
• Signoff flows and best practices

Materials / labs

• Designed lab exercises and automation scripts so students could run full flows with minimal setup friction.
• Provided templates for verification and backend flow orchestration.