CMS28v2 – AI In-Pixel Readout Chip for HL-LHC
Published:
CMS28v2: In-Pixel AI Readout Chip
| Field | Value |
|---|---|
| Project | CMS28v2 – AI In-Pixel Readout Chip for HL-LHC |
| Year | 2023 |
| Technology | 28nm CMOS |
| Type | ASIC |
| Role | Lead Digital Designer |
| Funding | CERN, Fermilab, Northwestern University, Columbia University |
| Collaborators | Giuseppe Di Guglielmo, Farah Fahim, others |
Project Overview
This project involved designing a complete radiation-hardened pixel ASIC for the HL-LHC CMS detector upgrade. The chip integrates on-sensor AI-based neural network classifiers to perform real-time data filtering and compression, reducing data bandwidth while maintaining physics performance.
Technical Details
- Neural Network Integration: Implemented ML inference using hls4ml framework integrated with Catapult HLS for hardware synthesis
- Latency Optimization: Achieved sub-10ns neural network inference latency to meet detector trigger timing
- Radiation Hardening: Applied TMR (Triple Modular Redundancy) and other hardening techniques for HL-LHC radiation environment
- Layout & Signoff: Full physical design from synthesis through DRC/LVS and timing closure
- Verification: Comprehensive RTL and post-layout verification including radiation upset simulation
Publications
- Parpillon et al. (2023). “Radiation-Hard Smart-Pixel Detector ASIC ReadOut with Digital AI in 28nm”
GitHub repository: [Add link when available]